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D a ta S h e e t , R ev . 1 . 5 1, J u n e 20 0 7
TLE 7263E
I n t e g r a t e d H S - C A N , L IN , L D O a n d HS Switch System Basis Chip
Automotive Power
Never stop thinking.
Integrated HS-CAN, LIN, LDO and HS Switch System Basis Chip
TLE 7263E
1
Features * * * * * * * * * * * * *
Overview
Two Low Drop Voltage Regulators Window watchdog Standard 16-bit SPI-interface Supports Controller Stop Mode Sleep Mode (50A) VBAT Monitoring and fail-safe output Overtemperature and short circuit protection Power on and undervoltage reset generator High side switch, 150 mA 4 Monitoring / wake-up inputs Exposed Pad Package AEC Qualified Green (RoHS Compliant) product
PG-DSO-36-24
HS CAN Transceiver * * * * * CAN data transmission rate up to 1 MBaud Low power mode management Supports sleep and receive-only modes Bus wake-up capability via CAN message Bus pins are short circuit proof to ground and battery voltage
LIN Transceiver * * * * * Single-wire transceiver Transmission rate up to 20 kBaud Compatible to LIN specification 1.3 and 2.0 Very low current consumption in Sleep Mode Short circuit proof to GND and battery
Type TLE 7263E
Data Sheet
Package PG-DSO-36-24
2
Marking
Rev. 1.51, 2007-06-22
TLE 7263E
Overview Dual-Voltage Regulator * * * Low-dropout voltage regulator, dual voltage-supply V1, 150 mA, 5 V 2% for external devices, e.g. microcontrollers V2, 150 mA, 5 V 2% for internal CAN module and external devices.
Description The TLE 7263E is a monolithic integrated circuit in an enhanced power package. The IC is designed for CAN-LIN gateway applications. To support these applications the TLE 7263E covers smart power functions such as HSCAN transceiver and LIN transceiver for data transmission, dual low dropout voltage regulator (LDO) for external 5 V supply, and high-side switch as well as a 16-bit SPI (serial peripheral interface) to control and monitor the IC. There is also a window watchdog circuit with a reset feature, a fail-safe output, a voltage sensing input and a undervoltage reset feature implemented. The device offer low power modes in order to support modules directly connected to the battery (KL. 30). A wake-up from the low power mode is possible via a message on the bus or via the bi level sensitive monitoring/wake-up inputs. The integrated High-Side switch can also be used to periodically supply an external wake-up circuitry in the low power mode, by choosing a special function. The integrated bus transceivers offer a receive-only mode for software diagnosis functions. The IC is designed to withstand the severe conditions of automotive applications.
Data Sheet
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Rev. 1.51, 2007-06-22
TLE 7263E
Pin Configuration
2
Pin Configuration
GND GND NC LIN MTS GND OUTHS VS MON1 MON2 MON3 MON4 SI GND VCC1 VCC2 INT GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35
GND TxDLIN RxDLIN FSO WKO CSN CLK DI DO STS RO RxDCAN TxDCAN GND CANL SPLIT CANH GND
TLE7263E DSO 36 - Exposed Pad
34 33 32 31 30 29
cooling tab (GND)
28 27 26 25 24 23 22 21 20 19
Pinnout_7263_SO-36EP
Figure 1
Pin Configuration (top view)
Data Sheet
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Rev. 1.51, 2007-06-22
TLE 7263E
Pin Configuration Table 1 Pin 9 10 11 12 8 Pin Definitions and Functions Symbol Function MON1, MON2, MON3, MON4 Monitoring / Wake-Up Inputs; bi level sensitive inputs used to monitor signals coming from, for example, an external switch panel; also used as wake-up input during cyclic sensing in low power modes (MON4 is exempted from "cyclic sense" as this input is permanently active) Power Supply Input; block to GND directly at the IC with ceramic capacitor; (ferrite recommended for better EMC behavior) Voltage Regulator Output (V1); 5 V supply; to stabilize block to GND with an external capacitor CQ 10 F, ESR < 6 Voltage Regulator Output (V2); 5 V supply; to stabilize block to GND with an external capacitor CQ 10 F, ESR < 6 Wake-Up Event Output; indicates wake up via monitoring inputs, CAN or LIN during Sleep or Stop Mode; active low; wake up sets device to Standby Mode Fail Safe Output; to supervise and control critical applications, high when watchdog is correctly served, low at any reset condition; active low Reset Output; open drain output, integrated pull-up, active low Sense Comparator Input; for monitoring of external voltages, to program the detection level connect external voltage divider Interrupt Output; output to monitor sense comparator input condition; input for enabling the Flash Programming Mode (voltage to be applied > 7 V) Master Termination Switch; output used to turn-on the termination/pull-up resistor of a LIN master LIN Transceiver Data Output; according to the ISO 9141 and LIN specification 1.3 and 2.0; push-pull output; LOW in dominant state LIN Transceiver Data Input; according to ISO 9141 and LIN specification 1.3 and 2.0
VS VCC1 VCC2
15
16
32
WKO
33
FSO
26 13
RO SI
17
INT
5 34
MTS RxDLIN
35
TxDLIN
Data Sheet
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TLE 7263E
Pin Configuration Table 1 Pin 4 29 LIN DISPI Pin Definitions and Functions (cont'd) Symbol Function LIN Bus; Bus Line for the LIN interface, according to ISO 9141 and LIN specification 1.3 and 2.0 SPI Data Input; receives serial data from the control device; serial data transmitted to DI is a 16-bit control word with the Least Significant Bit (LSB) transferred first: the input has a pull-down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal SPI Data Output; this tri-state output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN) SPI Clock Input; clock input for shift register; CLK has an internal pull-down and requires CMOS logic level inputs SPI Chip Select Not Input; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal pull-up and requires CMOS logic level inputs
28
DOSPI
30 31
CLKSPI CSNSPI
7
OUTHS High Side Switch Output; controlled via SPI, in SBC Sleep Mode controlled by internal cyclic sense function when selected TxDCAN RxDCAN SPLIT CANH CANL STS CAN Transmit Data Input; integrated pull-up CAN Receive Data Output CAN Termination Output; to support the recessive voltage level of the bus lines CAN High Line Output CAN Low Line Input Send-to-Sleep; to switch the SBC back into low current mode during cyclic wake Ground
24 25 21 20 22 27
GND 1, 2, 6,14, 18,19, 23,36 3 EP NC EP
Not Connected Internally; leave open or connect to GND Exposed Pad; internally connected to GND; connect to GND on board
Data Sheet
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Rev. 1.51, 2007-06-22
TLE 7263E
Block Diagram
3
VS
Block Diagram
OUTHS Interrupt control STS CSN
Drive + Protection INT SI Early Warning VS Supervisor
SPI
CLK DI DO VCC1
Over Current Over voltage Band Gap
+
Oscillator Timebase Reset Generator + Window Watchdog
V CC1
RO FSO
LDO 1
V CC2 Over Current Over voltage
LDO 2
MON1 MON2 MON3 MON4 CANH CANL
Wake-Up Logic
HS-CAN Mode Control V CC1
Output Stage
Driver Temp.Protection
Diagnosis Logic WKO
+ timeout
TxDCAN VCC1
SPLIT MUX RxDCAN
HS-CAN Transceiver
Receiver + Bus Failure Detection VS LIN Mode Control
Vs
MTS
Driver 30 kOhm LIN Output Stage Temp.Protection
V CC1
TxDLIN
Receiver Filter / Wake-Up RxDLIN
LIN Transceiver
GND
blockdiagramm7263
Figure 2
Data Sheet
Functional Block Diagram
7 Rev. 1.51, 2007-06-22
TLE 7263E
Features
4
Features
The TLE 7263E incorporates a lot of features, that are listed in Table 2 below. A short description of the features is given in "Operation Modes" on Page 9. Table 2 Feature Truth Table of the TLE 7263E SBC Active Mode ON ON ON ON ON ON ON OFF ON SBC Standby Mode ON ON/OFF ON ON ON ON ON ON OFF ON SBC Stop Mode ON ON/OFF ON ON/OFF ON ON ON ON ON ON ON OFF OFF OFF OFF active low wake-up interrupt active low wake-up interrupt active low early warning active low wake-up SBC Sleep Mode OFF OFF1) OFF OFF/[ON] OFF OFF ON OFF ON OFF ON OFF OFF OFF OFF low CAN RxD-only Mode ON ON ON ON ON ON ON ON OFF ON OFF OFF ON ON ON L/H
VCC, V1, 5 V VCC, V2, 5 V
Reset RO Fail Safe Output Sense input Monitoring pins HS-switch HS-cyclic-sense 16-bit SPI CAN/LIN wake-up via bus message CAN Transmit CAN Receive LIN Transmit LIN Receive RxDLIN
Window Watchdog ON
OFF/"Sleep" ON ON/"Sleep" ON/"Sleep" ON/"Sleep" ON/"Sleep" L/H OFF OFF OFF OFF active low wake-up interrupt active low wake-up interrupt active low early warning active low wake-up
RxDCAN
L/H
low
L/H
INT output
active low early warning OFF
low
active low early warning OFF
WKO output
low
1) In Sleep Mode the Vcc2 should be switched off. This is the default setting at the SPI
Data Sheet
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Rev. 1.51, 2007-06-22
TLE 7263E
Features
4.1
Operation Modes
This System Basis Chip (SBC) offers five main operation modes that are controlled via three mode select bits MS1, MS2 and MS3 within the SPI: SBC Active, Standby, Sleep and Stop mode, as well as CAN Receive-Only mode. After powering-up the SBC, it starts-up in SBC Standby Mode, waiting for the microcontroller to finish its startup and initialization sequences. From this transition mode the SBC can be switched via SPI command into the desired operating mode (The device should not be switched directly from Standby Mode to Sleep or Stop Mode). All modes are selected via SPI bits or certain operation conditions, e.g. external wake-up events. The SBC Active Mode, that is used in order to transmit and receive CAN and LIN messages, supports two additional sub-modes, "CAN Sleep" and "LIN Sleep". During these sub-modes the SBC remains its voltage regulators running in order to supply external devices. Also, the line termination of the "sleeping" bus transceiver is turned-off respectively. During SBC Sleep Mode, the lowest power consumption is achieved, by having its main voltage regulator switched-off. As the microcontroller can not be supplied, the integrated window watchdog might be disabled in Sleep Mode via SPI bit. However, it can be turned-on for periodically waking-up the system, e.g. ECU, by generating a reset. In case an external microcontroller needs to be supplied with its quiescent current, the SBC Stop Mode can be chosen. In this mode the main voltage regulator remains active. Optionally, the second voltage regulator can be turned-on or off via the SPI prior to entering one of the respective power saving modes. The integrated window watchdog remains active until the microcontroller enters its power saving mode ("Stop Mode"). This power saving mode is assumed to be reached once the current consumption is below a certain threshold (see Watchdog current threshold, Table and "Window Watchdog, Reset" on Page 26). In both low power modes the internal bus transceivers, including the line termination, are turned off while the wake-up capabilities via bus message or monitoring pins are still active. The SBC offers Sleep and Stop Mode in conjunction with or without the Cyclic Sense/Wake feature. If the Cyclic Sense/Wake feature is selected, two possible states can be entered during Sleep/Stop Mode: HS-On and HS-Off (see text and respective state diagram). The Cyclic Sense feature can be used to supply an external wake-up circuitry periodically, and is entered upon activation via SPI command. In cyclic sense HS-On state, the High-Side switch is activated for a certain "on-time" and provides supply voltage at its OUTHS pin. Within this on-time the SBC starts sampling of the monitoring/wake-up lines. On-time as well as time period are programmable via the SPI control word. A wake-up at the monitoring / wake-up pins during the on-time as well as a message at the CAN or LIN bus lines automatically sets the TLE 7263E into SBC Standby mode, and turns-on the main voltage regulator VCC1. The digital RxDCAN/RxDLIN lines, that are monitored by the microcontroller during power saving, are pulled low with
Data Sheet 9 Rev. 1.51, 2007-06-22
TLE 7263E
Features respect to the wake-up source (CAN or LIN). Furthermore, the wake-up source is indicated within the SPI status word. Additionally, the wake-up capabilities of the monitoring / wake-up pins can be configured via SPI. If Cyclic Wake is entered upon SPI command, the High-Side switch is turned-on immediately (HS-On state), providing supply voltage at the OUTHS pin. Once the HSOn state is entered, a transition to the HS-Off state can be triggered by a pulse with a minimum width at the STS pin (see STS pulse width, Table ). The microcontroller fully controls the signal level at the STS pin, and this way determines the duration of the HSOn state. As of now the HS-Off state is automatically terminated according to the Cyclic Wake period selected via SPI, or by a CAN or LIN message.
Start Up Power Up
SBC Standby Mode Vcc1 ON
SBC Stop Mode MS2 1 MS1 1 MS0 1 Vcc1 ON MS2 1
SBC Sleep Mode MS1 0 MS0 0 Vcc1 OFF
SBC Active Mode MS2 0 MS1 1 MS0 1 Vcc1 ON
SBC Active Mode: CAN Sleep" MS2 0 MS1 0 MS0 1 Vcc1 ON MS2 1
CAN RxD Only MS1 0 MS0 1 Vcc1 ON
SBC Active Mode: LIN Sleep" MS2 0 MS1 1 MS0 0 Vcc1 ON MS2 1
LIN RxD Only MS1 1 MS0 0 Vcc1 ON
modes_TLE7263
Figure 3
Functional Overview "SBC Operation Modes"
Data Sheet
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TLE 7263E
Features
4.2
SBC Sleep Mode without Cyclic Sense
In order to reduce the current consumption to a minimum, the SBC offers a Sleep Mode without Cyclic Sense (see Figure 4). This mode is entered via SPI command, and turnsoff the integrated bus transceivers and respective termination, main voltage regulator as well as the High-Side switch. Upon a voltage level change at the monitoring/wake-up pins or by a CAN or LIN message the SBC Sleep Mode will be terminated and the SBC Standby Mode will automatically be entered.
SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 Vcc1 ON
SBC Standby Mode Vcc1 ON
Start Up Power Up
Controller SPI-Command: - disable cyclic sense function" via SPI Timing Bits - select SBC Sleep Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [can remain active as periodic reset timer]
transition caused by: - event at MONx inputs - CAN message - LIN message [SPI indicates source]
Initialization of MONx inputs 1)
SBC Sleep Mode MS2 1 MS1 0 MS0 0 Vcc1 OFF
1) if initialization fails, device is switched into SBC Standby mode
HS-Switch = OFF
sleep_TLE7263
Figure 4
State Diagram "SBC Sleep Mode without Cyclic Sense"
Note: To switch into Low Power Mode from Standby Mode the device should be switched into Normal Mode first. This is required to reset the CAN and LIN transceiver to ensure correct wakeup as well as to ensure the correct function of the RO pin when going to Sleep Mode. The time the device is in Normal Mode before going to Low Power Mode should be long enough that the Vcc2 is up. This can be released by a wait time or by reading the status of Vcc2 via SPI (bit13).
Data Sheet
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TLE 7263E
Features
4.3
SBC Sleep Mode with Cyclic Sense
In order to reduce the current consumption to a minimum, but still supply a wake-up circuit periodically, the SBC offers a Sleep Mode with Cyclic Sense (see Figure 5). This mode is entered via SPI command, and turns-off the integrated bus transceivers and respective termination, as well as the main voltage regulator. The High-Side switch is turned-on according to the SPI timings setting for cyclic sense, as there is the cyclic sense period and the on-time. Upon a voltage level change at the monitoring/wake-up pins or by a CAN or LIN message the SBC Sleep Mode will be terminated and the SBC Standby Mode will automatically be entered. The respective RxD pin of the transceiver that generated the wake-up will be pulled low.
SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 Vcc1 ON
SBC Standby Mode Vcc1 ON
Start Up Power Up
Controller SPI-Command: - select cyclic sense period" via SPI Timing Bits - select HS-Switch on-time via SPI On-Time Bit" - select SBC Sleep Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [can remain active as periodic reset timer]
Initialization of MONx inputs 1)
transition caused by: - event at MON1 - 3 inputs [only during HS-ON state] - event at MON4 input - CAN message - LIN message [SPI indicates source]
SBC Sleep Mode MS2 1 MS1 0 MS0 0 Vcc1 OFF
HS-Switch = OFF
sense period"
after on-time"
HS cyclic sense MS2 1 MS1 0 MS0 0 Vcc1 OFF
1) if initialization fails, device is switched into SBC Standby mode
HS-Switch = ON
cyclic_sense_sleep_TLE7263
Figure 5
State Diagram "SBC Sleep Mode with Cyclic Sense"
Data Sheet
12
Rev. 1.51, 2007-06-22
TLE 7263E
Features
4.4
SBC Sleep Mode with Cyclic Wake
The SBC Sleep Mode has the advantage of reducing the current consumption to a minimum. During this mode the integrated voltage regulator for external supply is turned off. In case the connected microcontroller needs to get activated periodically, the Cyclic Wake feature in combination with the SBC Sleep Mode can be activated (see Figure 6).
SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 Vcc1 ON
SBC Standby Mode Vcc1 ON
Start Up Power Up
Controller SPI-Command: - select cyclic wake" via SPI Bit - select cyclic wake period" via SPI Timing Bits - select HS-Switch on-time via SPI On-Time Bit" - select SBC Sleep Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI
SBC Sleep Mode
Initialization of MONx inputs 1)
MS2 1
MS1 1
MS0 1
Vcc1 OFF
select SBC operating mode
HS-Switch = OFF
automatic transition by: - cyclic wake period - CAN message - LIN message
STS
C 2)
HS Cyclic Wake MS2 1
sampling of MON1...3 inputs [MON4 active permanently]
MS1 1
MS0 1
Vcc1 ON
WKO cyclic wake-up
HS-Switch = ON
1) if initialization fails, device is switched into SBC Standby mode
cyclic_wake_sleep_TLE7263
Figure 6
State Diagram "SBC Sleep Mode with Cyclic Wake"
Data Sheet
13
Rev. 1.51, 2007-06-22
TLE 7263E
Features
4.5
SBC Stop Mode without Cyclic Sense
The SBC Stop Mode has the advantage of reducing the current consumption to a minimum, while supplying the microcontroller with its quiescent current during its power saving mode ("Stop"). This mode is entered via SPI command, and turns-off the integrated bus transceivers and respective termination, but the main voltage regulator remains active. A voltage level change at the monitoring / wake-up pins will, in contrast to the behavior in Sleep Mode, generate a pulse at the WKO pin that is monitored by the microcontroller, e.g. at an external interrupt input. In case the wake-up event was a CAN or LIN message, the respective RxD pin will be pulled low. (The microcontroller itself has to take care of switching SBC modes after a wake-up event notification (see Figure 7).)
SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 Vcc1 ON
SBC Standby Mode Vcc1 ON
Start Up Power Up
Controller SPI-Command: - disable cyclic sense function" via SPI Timing Bits - select SBC Stop Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [off" once current consumption below threshold]
transition caused by: - event at MONx inputs - CAN message - LIN message [SPI indicates source]
Initialization of MONx inputs 1)
wake event notification [to C]: - CAN msg. => RxDCAN (low) - LIN msg. => RxDLIN (low) - MONx => WKO
SBC Stop Mode MS2 1 MS1 1 MS0 1 Vcc1 ON
1) if initialization fails, device is switched into SBC Standby mode
HS-Switch = OFF
stop_TLE7263
Figure 7
State Diagram "SBC Stop Mode without Cyclic Sense"
Data Sheet
14
Rev. 1.51, 2007-06-22
TLE 7263E
Features
4.6
SBC Stop Mode with Cyclic Sense
The SBC Stop Mode has the advantage of reducing the current consumption to a minimum, while supplying the microcontroller with its quiescent current during its power saving mode ("Stop"). This mode is entered via SPI command, and turns-off the integrated bus transceivers and respective termination, but the main voltage regulator remains active. The High-Side switch is turned-on according to the SPI timings setting for cyclic sense, as there is the cyclic sense period and the on-time. A voltage level change at the monitoring/wake-up pins will, in contrast to the behavior in Sleep Mode, generate a pulse at the WKO pin that is monitored by the microcontroller, e.g. at an external interrupt input. In case the wake-up event was a CAN or LIN message, the respective RxD pin will be pulled low. (The microcontroller itself has to take care of switching SBC modes after a wake-up event notification (see Figure 8).)
SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 Vcc1 ON
SBC Standby Mode Vcc1 ON
Start Up Power Up
Controller SPI-Command: - select cyclic sense period" via SPI Timing Bits - select HS-Switch on-time via SPI On-Time Bit" - select SBC Stop Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [off" once current consumption below threshold]
transition caused by: - event at MON1 - 3 inputs [only during HS-ON state] - event at MON4 input - CAN message - LIN message [SPI indicates source]
Initialization of MONx inputs 1)
SBC Stop Mode MS2 1 MS1 1 MS0 1 Vcc1 ON
wake event notification [to C]: - CAN msg. => RxDCAN (low) - LIN msg. => RxDLIN (low) - MONx => WKO
HS-Switch = OFF
"sense period"
after on-time"
1) if initialization fails, device is switched into SBC Standby mode
HS Cyclic Sense MS2 1 MS1 1 MS0 1 Vcc1 ON
HS-Switch = ON
cyclic_sense_stop_TLE7263
Figure 8
State Diagram "SBC Stop Mode with Cyclic Sense"
Data Sheet
15
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TLE 7263E
Features
4.7
SBC Stop Mode with Cyclic Wake
The SBC Stop Mode has the advantage of reducing the current consumption to a minimum, while supplying the microcontroller with its quiescent current during its power saving mode ("Stop"). This mode is entered via SPI command, and turns-off the integrated bus transceivers and respective termination, but the main voltage regulator remains active. In contrast to Cyclic Sense the HS-On state is entered once Cyclic Wake is selected, immediately providing supply voltage at the OUTHS pin. The microcontroller determines the duration of the HS-On state via the STS input pin (see Figure 9). Further transitions from that HS-Off into the HS-On state are done by the selected cyclic wake period or by a bus message. The microcontroller is notified by the WKO (Wake-Up Output) that the HS-On state has been entered. Further notification is done in the same way as for Cyclic Sense in Stop Mode.
SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 Vcc1 ON
SBC Standby Mode Vcc1 ON
Start Up Power Up
Controller SPI-Command: - select cyclic wake" via SPI Bit - select cyclic wake period" via SPI Timing Bits - select HS-Switch on-time via SPI On-Time Bit" - select SBC Stop Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [off" once current consumption below threshold]
SBC Stop Mode
Initialization of MONx inputs 1)
MS2 1
MS1 1
MS0 1
Vcc1 ON
select SBC operating mode
HS-Switch = OFF
automatic transition by: - cyclic wake period via STS pin - CAN message or - LIN message after on-time"
STS
C 2)
HS Cyclic Wake MS2 1
sampling of MON1...3 inputs [MON4 active permanently]
MS1 1
MS0 1
Vcc1 ON
WKO cyclic wake-up
HS-Switch = ON
C wake-up inputs
1) if initialization fails, device is switched into SBC Standby mode 2)
window watchdog activated automatically once current threshold is exceeded
cyclic_wake_stop_TLE7263
Figure 9
Data Sheet
State Diagram "SBC Stop Mode with Cyclic Wake"
16 Rev. 1.51, 2007-06-22
TLE 7263E
Features Continuous Timer Mode (CTM) for "Cyclic Wake Timer" Upon start of the "cyclic wake timer" in Cyclic Wake Mode the operating mode might be changed to "SBC Active Mode" by the microcontroller, e.g. in order to transmit data via the CAN or LIN transceiver. In this case the timer continues running with the selected period started in Cyclic Wake Mode. This behavior guarantees the periodic generation of a wake-up signal at the WKO pin, even in case of a mode switch. However, this provides that the time spent in SBC Active Mode is not exceeding the selected period. Should a time-out (end of selected period) occur in SBC Active Mode before the Cyclic Wake Mode is re-entered, the SBC will generate an interrupt signal at its WKO pin if the CTM feature is enabled via the respective SPI bit (see Figure 11). When the CTM feature is set in the SPI, a wake-up event at the CAN bus in "SBC Active CAN Sleep" mode or at the LIN bus in the "SBC Active LIN Sleep" mode results in switching WKO "low" in addition to switching the RxD to "low".
4.8
Dual Low Dropout Voltage Regulator
The dual low dropout voltage regulator integrated in the TLE 7263E is able to drive external as well as internal loads, e.g. CAN-circuit supplied via VCC2, even in case of a bus short circuit. Its output voltage tolerance is better than 2%. The maximum output current for external loads is limited to 150 mA (VCC1), e.g. for microcontroller supply, and 150 mA (VCC2) for internal CAN module and, e.g. for external sensor supply. The two voltage regulator outputs are protected against overload and overtemperature. The thermal pre-warning flag might be used by the microcontroller to reduce the power dissipation of the TLE 7263E by switching off functions of minor priority until the temperature threshold of the thermal shutdown is reached. An external reverse current protection is required at the pin VS to prevent the output capacitor from being discharged by negative transients or low input voltage. A capacitor of 10 F at the supply voltage input VS buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line. Stability of the output voltage is guaranteed for output capacitors CQ 100 nF, nevertheless it is recommended to use capacitors CQ 10 F to buffer the output voltage and therefore improve the reset behavior at input voltage transients.
Data Sheet
17
Rev. 1.51, 2007-06-22
TLE 7263E
Features
4.9
CAN Transceiver
The TLE 7263E is optimized for high speed data transmission up to 1 MBaud in automotive applications and is compatible to the ISO 11898 standard. It works as an interface between the CAN protocol controller and the physical bus lines. This HS-CAN module also supports extended bus error detection via a general error flag as well as individual notification flags, e.g. temperature shutdown and TxD time-out flag, within the SPI. To reduce EMI the dynamic slopes of the CANL and CANH signals both are limited and symmetric. This allows the use of an unshielded twisted or parallel pair of wires for the bus. Furthermore there is implemented a time-out feature to prevent the bus from being blocked by a permanently dominant TxD input signal. Both, the CANL and CANH output stage are automatically disabled after the delay time tTxD. In order to protect the transceiver output stages from being damaged by shorts on the bus lines, current limiting circuits are integrated. The CANL and CANH output stage respectively are protected by an additional temperature sensor, that disables them as soon as the junction temperature exceeds the maximum value. During the temperature shut-down condition of the CAN output stages receiving messages from the bus lines is still possible. Wake-Up Indication: A bus wake-up via a CAN message (minimum dominant time Vcc2, which supplies the CAN output stage is switched ON.The CAN transceiver has to be enabled to reset the wake-up capability after a bus wake event and after power-up. Bus Failure Flag: signalizes a bus line short circuit condition to GND, VS or VCCx via SPI bit 11 in the SPI Output Data "CAN Bus Failure". Remarks: Flag is set after four consecutive recessive to dominant cycles on pin TxD when trying to drive the bus dominant. The bus failure flag is cleared upon 4 recessive to dominant edges at TxD without failure condition. Local Failure Flag: signalizes the local failure conditions listed in the text below via SPI bit 10 in the SPI Output Data "CAN Local Failure". Remark: Flag is cleared upon dominant level at RxD while TxD is recessive. General: release of the transmitter stage only after transition into CAN RxD Only mode and transition back into SBC Active Mode. TxD Dominant Failure Detection At permanent dominant signal for t > tTxD at TxD the local failure flag is set and the transmitter stage is turned off. Remarks: none
t > tWU) from low power mode sets the RxD pin and the WKO pin to low. In addition, the
Data Sheet
18
Rev. 1.51, 2007-06-22
TLE 7263E
Features RxD Permanent Recessive Clamping Internal RxD signal does not match signal at RxD pin because the RxD pin is pulled to HIGH (permanent HIGH). This results in setting the local failure flag and disabling of the receiver stage Remark: the flag is cleared when RxD signal gets dominant. TxD to RxD Short Circuit Caused by a short circuit between RxD and TxD. The local failure flag is set and the transmitter stage is disabled. Remark: the flag is cleared once the short circuit condition is removed. Bus Dominant Clamping At a permanent dominant signal at the CAN bus for t > tBUS the local failure flag is set. Remark: none Over Temperature Detection Once the maximum junction temperature at the driving stages exceeded, the local failure flag is set and the transmitter stage is disabled. Remark: the flag is cleared once RxD gets dominant. Bus only released after the next dominant bit in TxD. Split Circuit The split circuitry is activated during SBC Active and RxD Only Mode and deactivated (SPLIT pin high omic) during SBC Sleep, Stop and Standby Mode. The SPLIT pin is used to stabilize the recessive common mode signal in SBC Active Mode and RxD Only mode. This is realized with a stabilized voltage of 0.5 VCC2 at the SPLIT pin. A correct application of the SPLIT pin is shown in Figure 10. The split termination for the left and right node is realized with two 60 Ohm resistances and one 10nF capacitor. The center node in this example is a stub node and the recommended value for the split resistances is 1.5 kOhm.
Data Sheet
19
Rev. 1.51, 2007-06-22
TLE 7263E
Features
CANH
CANH
TLE 7263 R
SPLIT
10nF
60Ohm
60Ohm
TLE 7263 R
SPLIT
10nF
split termination
60Ohm
CAN Bus
split termination
60Ohm
CANL
10nF
CANL split termination at stub
1,5 kOhm
1,5 kOhm
CANH
SPLIT
CANL
TLE 7263 R
Figure 10
Application of the SPLIT pin for normal nodes and one stub node
4.10
LIN Transceiver
The TLE 7263E offers a transceiver, which is compatible to ISO 9141 and LIN specification 2.0. For fail safe reasons the transceiver already has a pull-up resistor of 30 k implemented. In order to achieve the required timing for the dominant to recessive transition of the bus signal an additional external termination resistor of 1 k is required, when the LIN node is used as a master. This termination resistor will automatically be turned off via the "Master Termination Switch" pin (MTS) once the LIN module enters LIN Sleep Mode or when the SBC enters Sleep Mode. The transceiver is protected against short to battery and short to GND. For LIN automotive applications in the United States a dedicated mode by the name "Low Slope Mode" can be used. This mode limits the maximum data transmission rate to 10.4 kBaud by switching to a different slew rate. Operating with the default slew rate at up to 20 kBaud may cause interferences with the AM radio band. A bus wake-up via a LIN message (minimum dominant time t > twake) from low power mode sets the RxD pin and the WKO pin to low. in addition the MTS is switched ON. The LIN transceiver has to be enabled to reset the wake-up capability after a bus wake event and after power-up. In case of a "TxD dominant time out failure" or a "transmitter thermal shutdown" the SPI bit 9 is set. After a SPI read-out this bit will be reset unless one of the failure conditions is still present. Note: In case of a short to GND on the LIN bus a RxD dominant signal is generated by the SBC. In the case that RxD is dominant the device can not go into low power mode from normal mode.
Data Sheet 20 Rev. 1.51, 2007-06-22
TLE 7263E
Features
4.11
SPI (Serial Peripheral Interface)
The 16-bit wide Programming or Input Word (see Table 3) is read in via the data input DI, which is synchronized with the clock input CLK supplied by the C. The Diagnosis or Output Word appears synchronously at the data output DO (see Figure 10). The transmission cycle begins when the chip is selected by the Chip Select Not input CSN ("low" active). After the CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output switches to tristate status at this point, thereby releasing the DO bus for other usage. The state of DI is shifted into the input register with every falling edge on CLK. The state of DO is shifted out of the output register after every rising edge on CLK. The number of received input clocks is supervised by a modulo-16 operation and the Input / Control Word is discarded in case of a mismatch. This error is flagged by the WKO set to "low" and in the following SPI output by a "high" at the data output (DO pin) before the first rising edge of the clock is received.
MSB LSB
Input Data
15 14 13 12 11 10
9
8
7
6
5
4
CS1
3
CS0
2
MS2
1
MS1
0
MS0
WD VCC2 On/Off On/off
Configuration Registers
Res. SI MON4 MON3 MON2 MON1 LIN Reset Reset On/Off On/Off On/Off On/Off On/Off 10.4k Delay Thres.
Configuration Select
Mode Selection Bits not valid Active CAN Sleep Active LIN Sleep Active Sleep CAN RxD Only LIN RxD Only Stop
000
00
Reserved
Select OUTHS off" Cyclic Sense / Wake
OUTHS On/Off
01
001
CTM On/Off
OUTHS On-Time
Cyclic Sense / Wake Timing Bit Position: 9 .. 5 Window Watchdog Timing Bit Position: 10 .. 5
10
010
Reserved
0
11
011
(Watchdog Trigger Register)
100
101
110
111
SPI_Bit_Settings
Figure 11
16-Bit SPI Input Data / Control Word
Data Sheet
21
Rev. 1.51, 2007-06-22
TLE 7263E
Features Table 3 IBIT 0...2 3...4 5 ... 13 14 15 Table 4 MS2 0 0 0 0 1 1 1 1 Table 5 CS1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 SPI Input Data Bits Input Data Mode Selection Configuration Selection (determine meaning of "Configuration Setting Bits") Configuration Settings (meaning based on "Configuration Selection Bits")
VCC2 Activation (power saving modes only)
Window Watchdog "on"/"off" (power saving modes only) Mode Selection Bits MS1 MS0 0 1 0 1 0 1 0 1 Mode Selection: SBC Mode "reserved" / not valid SBC Active Mode: "CAN Sleep" SBC Active Mode: "LIN Sleep" SBC Active Mode (CAN & LIN "on") SBC Sleep (CAN, LIN & VReg "off") SBC Active mode : CAN Transceiver: RxD-Only SBC Active mode : LIN Transceiver: RxD-Only SBC Stop Mode (CAN & LIN "off")
Configuration Selection Bits CS0 Configuration Selection General Configuration Integrated Switch Configuration Cyclic Sense / Wake Configuration Window Watchdog Configuration
Data Sheet
22
Rev. 1.51, 2007-06-22
TLE 7263E
Features Table 6 Pos. 5 General & Integrated Switch Configuration General Configuration1) Reset Threshold (see Table : "Reset Generator", "0" = VRT1 / "1" = VRT2) LIN "Low Slope Mode" (10.4 kBaud) MON1 Input Wake-Up Capability MON2 Input Wake-Up Capability MON3 Input Wake-Up Capability MON4 Input Wake-Up Capability Sense Input (SI) "on" / "off" "reserved" / not used Integrated Switch Configuration2) OUTHS "on" / "off"
6 7 8 9 10 11 12 13
Reset Delay ("0" = 5 ms / "1" = 0.5 ms) "reserved" / not used "reserved" / not used "reserved" / not used "reserved" / not used "reserved" / not used "reserved" / not used "reserved" / not used "reserved" / not used
1) "1" = ON (enable), "0" = OFF (disable) 2) "1" = ON, "0" = OFF
Table 7 Pos. 5 6 7 8 9 10 11 12
Cyclic Sense / Wake & Window Watchdog Period Settings1) Cyclic Sense / Wake Configuration Cyclic Period Bit 0 (T0) Cyclic Period Bit 1 (T1) Cyclic Period Bit 2 (T2) Cyclic Period Bit 3 (T3) Cyclic Period Bit 4 (T4) Window Watchdog Configuration Watchdog Period Bit 0 (T0) Watchdog Period Bit 1 (T1) Watchdog Period Bit 2 (T2) Watchdog Period Bit 3 (T3) Watchdog Period Bit 4 (T4)
Cyclic Sense / Wake Selection Watchdog Period Bit 5 (T5) ("0" = Cyclic Sense / "1" = Cyclic Wake) OUTHS On-Time Selection ("0" = 500 s / "1" = 100 s) "0" [mandatory]
Cyclic Wake Mode only: "reserved" / not used Select OUTHS "off" via STS / On-Time ("0" = via STS / "1" = via HS On-Time) Continuous Timer Mode (incl. WKO) ("0" = "off" / "1" = "on" ) "reserved" / not used
13
1) "1" = ON, "0" = OFF
Data Sheet
23
Rev. 1.51, 2007-06-22
TLE 7263E
Features Table 8 T4 0 0 0 0 0 0 0 ... 1 Table 9 T5 0 0 0 0 0 0 0 0 1 T4 0 0 0 0 0 0 0 ... 1 T3 0 0 0 0 0 0 0 ... 1 Cyclic Sense / Wake Period Settings T2 0 0 0 0 1 1 1 ... 1 T1 0 0 1 1 0 0 1 ... 1 T0 0 1 0 1 0 1 0 ... 1 Cyclic Sense or Cyclic Wake Period Cyclic Sense / Wake "off" 16 ms 32 ms 48 ms 64 ms 80 ms 96 ms ... ms 496 ms
Window Watchdog Reset Period Settings T3 0 0 0 0 0 0 0 ... 1 T2 0 0 0 0 1 1 1 ... 1 T1 0 0 1 1 0 0 1 ... 1 T0 0 1 0 1 0 1 0 ... 1 Window Watchdog Reset Period "not a valid selection" 16 ms 32 ms 48 ms 64 ms 80 ms 96 ms ... ms 1008 ms
Data Sheet
24
Rev. 1.51, 2007-06-22
TLE 7263E
Features Table 10 Pos. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SPI Output Data Output Data "after wake-up"2)
Output Data "active"1)
VCC1 Temperature Prewarning
HS Overcurrent OUTHS UV / Temp. Shut-Down Window Watchdog Reset MON1 Logic Input Level MON2 Logic Input Level MON3 Logic Input Level MON4 Logic Input Level MONx Initialization Failure LIN Failure CAN Local Failure CAN Bus Failure
VCC1 Temperature Prewarning
HS Overcurrent OUTHS UV / Temp. Shut-Down Window Watchdog Reset Wake-Up via MON1 Wake-Up via MON2 Wake-Up via MON3 Wake-Up via MON4 MONx Initialization Failure Bus Wake-Up via LIN Msg. Bus Wake-Up via CAN Msg. End of Cyclic Wake Period
VCC1 Fail (active low) VCC2 Fail (active low) VINT Fail (active low)
"reserved" / not used
VCC1 Fail (active low) VCC2 Fail (active low) VINT Fail (active low)
"reserved" / not used
1) "1" = ON (enable), "0" = OFF (disable) 2) "1" = ON, "0" = OFF
Data Sheet
25
Rev. 1.51, 2007-06-22
TLE 7263E
Features
4.12
Window Watchdog, Reset
When the output voltage Vcc1 exceeds the reset threshold voltage the reset output RO is switched HIGH after a delay time of typ. 5 ms. This is necessary for a defined start of the microcontroller when the application is switched on. As soon as an undervoltage condition of the output voltage (VCC1 < VRT) appears, the reset output RO is switched LOW again. The LOW signal is guaranteed down to an output voltage VCC1 1 V. Please refer to Figure 19, Reset Timing Diagram. After the above described delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is started by opening a long open window of typ. 64 ms. The long open window allows the microcontroller to run its initialization sequences and then to trigger the watchdog via the SPI. A watchdog trigger is detected as a write access to the "window watchdog period bit field" within the SPI control word. In order to distinguish the watchdog from the cyclic sense/wake timing register the "Configuration Select Bits" needs to be set accordingly (see "SPI (Serial Peripheral Interface)" on Page 21). The trigger is accepted when the CSN input becomes HIGH after the transmission of the SPI word. A correct watchdog trigger results in starting the window watchdog by opening a closed window with a width of 50% of the selected window watchdog reset period. This period, selected via the window watchdog timing bit field, is in the range between 16 ms and 1008 ms. This closed window is followed by a open window, with a width of 50% of the selected period. From now on the microcontroller has to service the watchdog by periodically writing to the window watchdog timing bit field. This write access has to meet the open window. A correct watchdog service immediately results in starting the next closed window (see Figure 17 "Watchdog Time-Out Definitions" on Page 54, safe trigger area). Should the trigger signal not meet the open window a watchdog reset is created by setting the reset output RO low (see Reset delay time tRD). Then the watchdog again starts by opening a long open window. In addition, a "window watchdog reset flag" is set within the SPI until the next successful watchdog trigger to monitor a watchdog reset. For fail safe reasons the TLE 7263E is automatically switched in SBC Standby mode if a watchdog trigger failure occurs. This minimizes the power consumption in case of a permanent faulty microcontroller. In case of a watchdog reset the watchdog immediately starts with a long open window in SBC Standby Mode. When entering a low power mode the watchdog can be requested to be disabled via an SPI bit (see "SPI (Serial Peripheral Interface)" on Page 21). Upon this request the watchdog is only turned off once the current consumption at VCC1 falls below the "watchdog current threshold".
Data Sheet
26
Rev. 1.51, 2007-06-22
TLE 7263E
Features
4.13
Sense Comparator using Sense Input SI and Interrupt Output INT
The sense comparator (early warning function) compares a voltage defined by the user to an internal reference voltage. Therefore the voltage to be supervised has to be scaled down by a voltage divider in order to compare it to the internal sense threshold VSIth. This feature can be used e.g. to supervise the battery voltage in front of the reverse protection diode. The microcontroller is given a prewarning before an undervoltage reset due to low input voltage occurs. The prewarning is flagged by setting the interrupt output INT low in SBC Active, Standby, and Stop, as well as in CAN Receive - Only Mode, when activated by SPI. In SBC Sleep Mode the sense function is inactive. Calculation of the voltage divider can be easily done since the sense input current can be neglected. An internal blanking time prevents from false triggering due to line transients. Further improvement is possible by the use of an external ceramic capacitor at the SI pin (see Figure 22, Application Circuit).
4.14
VINT/VCC Fail Detection via SPI Bit
Should the internal supply voltage become lower than the internal threshold VINT, th (typ. 2.5 V) the VINT-Fail, threshold SPI bit will be reset in order to indicate the low voltage condition. All other SPI settings are also reset by this condition. The VINT Fail feature can also be used to give an indication when the ECU has been changed and therefore a presetting routine of the microcontroller has to be started. Further there is also a VCC monitor implemented, where the VCCx is compared to the threshold voltage VCCx-Fail, threshold and the VCC SPI bit is reset accordingly. This monitoring is only available during voltage-regulator operation.
4.15
Monitoring / Wake-Up Inputs MON1/2/3/4 and Wake-Up Output WKO
In addition to a wake-up from SBC Sleep mode via the CAN or LIN bus lines it is also possible to wake-up the TLE 7263E from low power mode via the monitoring/wake-up inputs. These inputs are sensitive to a transition of the voltage level, either from high to low or vice versa. Monitoring is available in Active Mode and indicates the voltage level of the inputs. A positive or negative voltage edge at MONx in SBC Sleep or Stop Mode results in setting the output WKO low to signal a wake-up. After a wake-up via MONx the first transmission of the SPI diagnosis word in SBC Standby mode indicates the wake-up source. Further SPI status word transmissions show the logic level of the monitoring inputs. When switching the TLE 7263E into SBC Sleep mode (cyclic sense feature activated) the voltage level at the wake-up inputs is sensed 2 times to initialize the reference voltage. Should this initialization fail (2 samples are unequal) the device is automatically
Data Sheet 27 Rev. 1.51, 2007-06-22
TLE 7263E
Features set in SBC Standby mode and the initialization error is shown indicated in the SPI status word. To have a defined level at a floating MONx pin a hold current is implemented. For high level at MONx a pull up current IPU,MON is driven out of the MONx pin, for low level at MONx a pull down current IPD,MON is drawn into the MONx pin.
4.16
High Side Switch
The high side output OUTHS is able to switch loads up to 150 mA. Its on-resistance is 2.5 typ. @ 25 C. In SBC Active, Standby, as well as in CAN and LIN Receive-Only mode the high side output is switched on and off, respectively via an SPI input bit. To supply external wake-up circuits in SBC Sleep Mode the output OUTHS can be periodically switched on by the TLE 7263E itself. How Cyclic Sense works and how it is activated is described in detail in "Operation Modes" on Page 9. Beside the cyclic sense period can the on-time of the OUTHS be programmed to either 500 s (default setting) or 100 s via SPI input bit. OUTHS undervoltage, temperature shutdown, overcurrent as well as a temperature pre-warning is indicated by the SPI status word. The OUTHS is protected against short circuit and overload. As soon as the undervoltage condition of the supply voltage is met (VS < VUVOFF), the switch is automatically disabled by the undervoltage lockout circuit. Moreover the switch is automatically disabled when a reset or watchdog reset occurs.
4.17
Fail Safe Feature
The output FSO becomes HIGH when the watchdog is correctly serviced by the microcontroller for the fourth time. As soon as either an undervoltage reset or watchdog reset occurs, it is set LOW again. This feature is very useful to control critical applications independent of the microcontroller e.g. to disable the power supply in case of a microcontroller failure.
4.18
Send to Sleep Input STS
During Cyclic Wake the STS input is used to switch the SBC back to a low current mode (High-Side switch "off") when the microcontroller has completed its tasks during the periodic wake-up phase, and before it enters its power saving mode ("Stop") again.
4.19
Flash Program Mode
For flash programming it is useful to disable the window watchdog function. This can be done by applying a voltage of VINT > 7.0 V at pin INT. This is useful e.g. if the flashmemory of the micro has to be programmed and therefore a regular watchdog triggering is not possible.
Data Sheet
28
Rev. 1.51, 2007-06-22
TLE 7263E
Features Additionally, the transmission rate of the integrated LIN transceiver will be changed to maximal 150 kBaud. The Sense Comparator using Sense Input and Interrupt Output INT can not be used with Flash Program Mode. The Sense Input feature must be switched off via SPI. Hints for Unused Pins * * * * * SI: connect to GND OUTHS: leave open MON1/2/3/4: connect to GND INT / WKO: leave open RO / FSO: leave open
Data Sheet
29
Rev. 1.51, 2007-06-22
TLE 7263E
General Product Characteristics
5
5.1
Table 11 Parameter Voltages
General Product Characteristics
Maximum Ratings
Absolute Maximum Ratings Symbol Limit Values Min. Max. 40 5.5 40 40 40 V V V V V V - - - - - - 0 VSupply voltage Regulator output voltage CAN bus voltage (CANH, CANL) Input voltage at SPLIT Input voltage at MONx and SI Output voltage at OUTHS and MTS Logic input voltages (DI, CLK, CSN, STS, TxD) Logic output voltage (DO, RO, INT, RxD, FSO, WKO) Input voltage at Pin INT LIN line bus input voltages ESD resistivity ESD at RxD pin versus GND
VS VCC1, VCC2 VCANH/L VSPLIT VWK/SI VO VI VDRI,RD VINT Vbus
-0.3 -0.3 -27 -27 -27 -27 -0.3 -0.3 -27 -27
VS + 0.3
VCC + 0.3 V VCC + 0.3 V
40 40 1.5 2 6 V V kV kV kV
VESD,RxD -2 ESD all other pins. versus GND VESD1 -2 ESD at pin CANH, CANL, VESD1 -6
SPLIT, LIN, MONx versus GND Temperatures Junction temperature Storage temperature
Tj Tstg
-40 -50
150 150
C C
- -
1) ESD susceptibility HBM according to EIA/JESD 22-A 114B.
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
Data Sheet 30 Rev. 1.51, 2007-06-22
TLE 7263E
General Product Characteristics
5.2
Table 12 Parameter
Operating Range
Operating Range Symbol Limit Values Min. Max. V V V/s V nF MHz C After VS rising above VUV ON 40 V load dump - - ESR < 6 @ f = 10 kHz - - Unit Remarks
Supply voltage Supply voltage Supply voltage slew rate Logic input voltage (DI, CLK, CSN, TxD, STS) Output capacitor SPI clock frequency Junction temperature
VS VS
dVS/dt
VUV OFF 27 VUV OFF 40
-0.5 -0.3 100 - -40 5
VI CCC1/2 fclk Tj
VCC1
- 4 150
5.3
Parameter
Thermal Resistance
Symbol Min. Limit Values Typ. 1 25 Max. 5 K/W K/W
2)
Unit Remarks
Junction to Case1) Junction to Ambient1)
RthjC RthjA
1) Not subject to production test, specified by design. 2) According to Jedec JESD51-2,-5,-7 at natural convection on 2s2p board for 1W. Board: 76.2x114.3x1.5mm with 2 inner copper layers (70m thick)., with thermal via array under the exposed pad contacted the first inner copper layer
Data Sheet
31
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics
6
Table 13
Electrical Characteristics
Electrical Characteristics
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Quiescent Current; Pin VS Current consumption Typ. 6 1.2 1.7 4 Current consumption Max. 8 2 3 6 80 900 mA mA mA mA A A SBC Active Mode Active [CAN Sleep] => LIN dominant; without RL Active [LIN Sleep] stand-by mode; Tj = 25 C; VCC2 "off" stand-by mode; Tj = 25 C; VCC2 "off"; after LIN wake-up / power-up stop mode; Tj = 25 C; VCC2 "off"; without cyclic sense stop mode; Tj = 85 C; VCC2 "off"; without cyclic sense sleep mode; Tj = 25 C; VCC2 "off"; without cyclic sense sleep mode; Tj = 85C; VCC2 "off"; without cyclic sense sleep mode, during HS-On phase; Tj = 25 C; VCC2 "off" Unit Test Condition
IQ
-
IQ IQ
- -
68 580
Current consumption
IQ IQ IQ IQ IQ
-
68
80
A
Current consumption
-
76
88
A
Current consumption
-
49
60
A
Current consumption
-
53
65
A
Current consumption
-
220
300
A
Data Sheet
32
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Current consumption Symbol Limit Values Min. Typ. 240 Max. 330 A sleep mode, during HS-On phase; Tj = 85C; VCC2 "off" - Unit Test Condition
IQ
Voltage Regulator; Pin VCC1/2 Output voltage Line regulation Load regulation Power supply ripple rejection
VCC1/2
VCC1/2 VCC1/2
4.9 - - -
5.0 - - 40
5.1 20 50 -
V mV mV dB
1 mAPSRR
Vr = 1 Vpp; fr = 100 Hz;
specified by design; not subject to production test
Output current limit
ICC1/2max 200
-
500
mA
power transistor thermally monitored; 150 mA for external load - 0.5 V
VCC1/2 = 4.5 V;
Drop voltage
VDR
-
ICC1/2 = 150 mA;
internal modules not supplied; 4.5V < VS < 5.4V
Data Sheet
33
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Oscillator Oscillating frequency Internal cycling time (1/128 x fOSC) Symbol Limit Values Min. Typ. 256 500 Max. - 600 kHz s - - Unit Test Condition
fOSC tCYL
- 400
Reset Generator; Pin RO Reset threshold voltage VRT1 Reset threshold hysteresis Reset low output voltage 4.5 3.2 - - 4.65 3.35 100 0.2 4.8 3.5 - 0.4 V V mV V default SPI setting SPI option; VS 4 V -
VRT2 VRT,hys VRO
IRESET = 1 mA for VCC1 = VRT1/2 ; IRESET = 200 A for VRT1/2> VCC1 1 V
-
Reset high output voltage Reset pull-up current Reset reaction time Reset delay time
VRO IRO tRR tRD1 tRD2
0.7 x
- 150 10 5.0 0.5 4 0.2
VCC1
20 4 4.0 0.4 - -
+ 0.1 500 26 6.0 0.6 - 0.4 A s ms ms - V
VCC1
V
VRO = 0 V VCC1 < VRT1/2
to RO = L default SPI setting; after Power-On-Reset SPI setting option -
Fail Safe Output; Pin FSO Watchdog edge count difference to set HIGH Fail Safe low output voltage
nFS VFS
Fail Safe high output voltage
Data Sheet
VFS
VCC0.6
-
VCC + V
0.1
IFSO = 1 mA for VCC1 = VRT1/2 or IFSO = 200 A for VCC1 1 V IFSO = -1 mA for VCC1 VRT1/2
Rev. 1.51, 2007-06-22
34
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Sense In threshold voltage Sense In threshold hysteresis Sense reaction time Interrupt Out high voltage Interrupt Out low voltage Input voltage for Flash Programming Mode at pin INT voltage Typ. 2.3 200 10 - - 150 - Max. 2.8 300 20 V mV s V V A V Unit Test Condition
Sense Input (Early Warning) SI, VCCx-Fail, Interrupt Output INT
VSI,th VSI,hys tS,r VINThigh VINTlow
1.8 100 5 0.7 x
VSI decreasing
-
VSI < VSI,th to
INT = low
VCC1
0 20 7
VCC1
1.2 500 -
I0 = -20 A I0 = 1.25 mA VINT = 0 V
Interrupt pull-up current IINT
VINT VVCC1,th tVCC1,r tLW tWDR1 tWDR2 IWD,th
VCC1-Fail threshold VCC1-Fail reaction time
2.1 10 51 3.6 0.5
2.6 20 64 5.0 -
3.1 30 77 6.0 0.6 8
V s ms ms ms mA
- - - default SPI setting SPI setting option -
Watchdog Generator Long open window (128 cyl.) Watchdog reset-pulse Watchdog current threshold MONx input threshold voltage Input hysteresis
0.012 0.5
Monitoring Inputs MONx
VMONxth VI, hys.
2 0.1
3 -
4 0.7
V V
-
Data Sheet
35
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Pull up current Pull down current MONx filter time Input current Symbol Limit Values Min. Typ. -10 10 - - Max. -3 30 20 2 A A s A VMON = 3.8V VMON = 2V - VMONx > 5V 2.5 - 3.5 6.0 V A s s A s V V V ms -30 3 10 -2 Unit Test Condition
IPU,MON IPD,MON tMONx, f IMONx
VMONx = 0 V;
High Side Output OUTHS Static Drain-Source ON-Resistance; IOUTH = -150 mA Active Zener voltage Leakage current Switch ON delay time Switch OFF delay time Overcurrent shutdown threshold Shutdown filter time
RDSON HS -
-
Tj = 25 C
-
VOUTHS IQLHS tdONHS tdOFFHS ISDHS
- -10 - - -0.8 10 - 4.50 0.1 -
VS-45 -
- - - -0.4 25 5.35 4.85 0.2 16 to 512 - 20 20 -0.2 40 6.00 - - -
IOUTHS = -0.15 A VOUTHS = 0 V
CSN high to OUTHS CSN high to OUTHS - -
tdSDHS UV-Switch-ON voltage VUV ON UV-Switch-OFF voltage VUV OFF UV-ON/OFF-Hysteresis VUV HY Cyclic sense period tP CS
VS increasing VS decreasing VUV ON - VUV OFF
selectable via SPI bits; tolerance depending on internal oscillator default SPI setting SPI option
Cyclic sense ON time
tCS on1 tCS on2
0.4 0.08
0.5 0.1
0.6 0.12
ms ms
Data Sheet
36
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Send to Sleep Input (STS) H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Typ. - - - 40 - - - Max. 0.7 x V V V k s V V - - - Unit Test Condition
VIH VIL VIHY
- 0.3 x
VCC1
- 1.5 80 - - 0.2 x
VCC1
0.8 20 10
Pull-down resistance at RISTS pin STS STS pulse width HIGH level output voltage LOW level output voltage
VSTS = 0.2 x VCC1
one oscillator period
tSTS VWKO,H VWKO,L
Wake Event Output WKO 0.8 x
VCC1
-
IWKO = -1.6 mA IWKO = 1.6 mA
VCC1
CAN Transceiver Characteristics Receiver Output RxD HIGH level output current LOW level output current
IRD,H IRD,L
- 2
-4 4
-2 -
mA mA
VRD = 0.8 x VCC1; Vdiff < 0.4 V1) VRD = 0.2 x VCC1; Vdiff > 1 V1)
recessive state - dominant state -
Transmission Input TxD HIGH level input voltage VTD,H threshold - - 0.3 x 0.5 x
VCC1
0.7 x
V V V k
VCC1
- - 40
VTD,hys LOW level input voltage VTD,L
TxD input hysteresis threshold TxD pull-up resistance
0.4 0.5 x
VCC1
10
VCC1
20
RTD
Data Sheet
37
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter CAN Bus Receiver Differential receiver threshold voltage, recessive to dominant edge Differential receiver threshold voltage, dominant to recessive edge Common Mode Range Differential receiver hysteresis CANH, CANL input resistance Differential input resistance Wake-up Receiver threshold voltage, recessive to dominant edge Wake-up Receiver threshold voltage, dominant to recessive edge Wake-up Receiver differential receiver hysteresis Symbol Limit Values Min. Typ. 0.80 Max. 0.90 V Unit Test Condition
Vdiff,d
-
Vdiff = VCANH - VCANL
"active mode"
Vdiff,r
0.50
0.60
-
V
Vdiff = VCANH - VCANL
"active mode"
CMR
-12 - 10 20 -
- 110 20 40 0.8
12 - 30 60 1.15
V mV k k V
- "active mode" recessive state recessive state "sleep/stop mode"
Vdiff,hys Ri Rdiff Vdiff, d
Vdiff, r
0.4
0.7
-
V
"sleep/stop mode"
Vdiff, hys.
-
120
-
mV
"sleep/stop mode"
Data Sheet
38
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter CAN Bus Transmitter CANL/CANH recessive VCANL/H output voltage CANH, CANL recessive Vdiff output voltage difference Vdiff = VCANH - VCANL CANL dominant output voltage 2.0 -500 - - 3.0 50 V mV no load Symbol Limit Values Min. Typ. Max. Unit Test Condition
VTxD = VCC1;
no load
VCANL
0.5 2.75 1.5
- - -
2.25 4.5 3.0
V V V
CANH dominant output VCANH voltage CANH, CANL dominant Vdiff output voltage difference Vdiff = VCANH - VCANL CANH short circuit current CANL short circuit current Leakage current
VTxD = 0 V; VCC2 = 5 V VTxD = 0 V; VCC2 = 5 V VTxD = 0 V; VCC2 = 5 V VCANHshort = 0 V VCANLshort = 18 V VS = VCC2 = 0 V; 0 V < VCANH,L< 5 V
normal mode; -500 A < ISPLIT < 500 A standby mode; -22 V < VSPLIT < 35 V -
ICANHsc ICANLsc ICANH,lk ICANL,lk VSPLIT ISPLIT
-200 50 -
-80 80 25
-50 200 -
mA mA A
Split Termination Output; Pin SPLIT Split output voltage 0.3 x
VCC2
-5 -
0.5 x
VCC2
0 600
0.7 x
V
VCC2
5 -
Leakage current
A
SPLIT output resistance RSPLIT
Data Sheet
39
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Propagation delay td(L),TR TxD-to-RxD LOW (recessive to dominant) Propagation delay td(H),TR TxD-to-RxD HIGH (dominant to recessive) Propagation delay TxD LOW to bus dominant Propagation delay TxD HIGH to bus recessive Propagation delay bus dominant to RxD LOW Propagation delay bus recessive to RxD HIGH Min. dominant time for bus wake-up TxD permanent dominant disable time - Typ. 150 Max. 255 ns Unit Test Condition
Dynamic CAN-Transceiver Characteristics
-
150
255
ns
td(L),T td(H),T td(L),R
-
50
120
ns
-
50
120
ns
-
100
135
ns
td(H),R
-
100
135
ns
CL = 47 pF; RL = 60 ; VCC1/2 = 5 V; CRxD = 20 pF CL = 47 pF; RL = 60 ; VCC1/2 = 5 V; CRxD = 20 pF CL = 47 pF; RL = 60 ; VCC1/2 = 5 V CL = 47 pF; RL = 60 ; VCC1/2 = 5 V CL = 47 pF; RL = 60 ; VCC1/2 = 5 V; CRxD = 20 pF CL = 47 pF; RL = 60 ; VCC1/2 = 5 V; CRxD = 20 pF
- -
tWU tTxD
1 0.3
3 -
5 1.0
s ms
Data Sheet
40
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. LIN Transceiver Characteristics Receive Output RxD HIGH level output voltage LOW level output voltage Typ. Max. Unit Test Condition
VRxD,H VRxD,L
0.8 x
- -
- 0.2 x
V V
VCC1
-
VCC1
IRxD(LIN) = -1.6 mA; Vbus = VS IRxD(LIN) = 1.6 mA; Vbus = 0 V
recessive state - dominant state
Transmission Input TxD HIGH level input voltage VTxD,H threshold - 0.8 0.3 x - 40 - 0.7 x V V V k V
VCC1
1.5
VTxD,hys LOW level input voltage VTxD,L
TxD input hysteresis threshold TxD pull-up Resistor Bus Receiver Receiver threshold voltage, recessive to dominant edge Receiver dominant state Receiver threshold voltage, dominant to recessive edge Receiver recessive state
- 80
VCC1
20 0.42 x VS - -
RTxD Vbus,rd Vbusdom Vbus,dr Vbusrec
VTxD = 0 V
-
0.48 x -
VS
-
0.40 x VS
V V
(LIN Spec 1.3 (2.0); Line 10.1.9 (3.1.9))
0.52 x 0.58 x VS VS - -
Vbus,rec < Vbus < 27 V
0.6 x
-
VS
(LIN Spec 1.3 (2.0); Line 10.1.10 (3.1.10)) (LIN Spec 1.3 (2.0); Line 10.1.11 (3.1.11))
Receiver center voltage Vbuscent Receiver hysteresis
0.475 0.5 x x VS VS 0.02 x VS
0.525 V x VS V
Vbus,hys
0.04 x 0.1 x
VS
VS
Vbus,hys = Vbus,rec - Vbus,dom
(LIN Spec 1.3 (2.0); Line 10.1.12 (3.1.12))
Data Sheet
41
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Wake-up threshold voltage Bus Transmitter Bus serial diode voltage Vserdiode drop Bus dominant output voltage 0.4 - 0.7 - 1.0 1.2 V V Symbol Limit Values Min. Typ. 0.5 x Max. 0.6 x V - 0.40 x VS Unit Test Condition
Vwake
VS
VS
VTxD = high Level VTxD = 0 V; VS = 7 V; RL = 500 ;
(LIN Spec 1.3; Line 10.1.13)
Vbus,dom
-
-
2.0
V
VS = 18 V; RL = 500 ;
(LIN Spec 1.3; Line 10.1.14)
Bus dominant output voltage
Vbus,dom
0.6
-
-
V
VTxD = 0 V; VS = 7 V; RL = 1 k;
(LIN Spec 1.3; Line 10.1.15)
0.8
-
-
V
VS = 18 V; RL = 1 k;
(LIN Spec 1.3; Line 10.1.16)
Bus short circuit current Ibus,sc
40
100
150
mA
(LIN Spec 1.3 (2.0); Line 10.1.4 (3.1.4))
Vbus,short = 18 V
Data Sheet
42
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Leakage current Symbol Limit Values Min. Typ. -140 Max. - A -500 Unit Test Condition
Ibus,lk
VS = 0 V; Vbus = -8 V
(LIN Spec 1.3 (2.0); Line 10.1.7 (3.1.7)) (LIN Spec 1.3 (2.0); Line 10.1.8 (3.1.8))
-
10
25
A
VS = 0 V; Vbus = 18 V VS = 18 V; Vbus = 0 V VBUS =18V VS = 8V
-1
-
-
mA
(LIN Spec 1.3 (2.0); Line 10.1.5(3.1.5)) - - 20 A (LIN Spec 1.3 (2.0); Line 10.1.6 (3.1.6)) Bus pull-up resistance
Rbus Ilin
20
30
60
k
Active/Standby mode (LIN Spec 1.3 (2.0); Line 10.2.2 (3.2.2)) Sleep mode;Vbus = 0V
LIN output current
5
20
60
A
Data Sheet
43
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Dynamic Transceiver Characteristics Slew rate falling edge Typ. - Max. -1 V/s 60% > Vbus > 40% 1 s < ( = Rl x Cbus) < 5 s; VS = 13.5 V; Active mode (LIN Spec 1.3; Line 10.3.1) V/s 40% < Vbus < 60% 1 s < ( = Rl x Cbus) < 5 s; VS = 13.5 V; Active mode. (LIN Spec 1.3; Line 10.3.1) s Unit Test Condition
Sfslope
-3
Slew rate rising edge
Srslope
1
-
3
Slope symmetry
tslopesym
-5
-
5
tfslope - trslope; VS = 13.5 V
(LIN Spec 1.3; Line 10.3.3)
Propagation delay TxD LOW to bus Propagation delay TxD HIGH to bus Propagation delay bus dominant to RxD LOW Propagation delay bus recessive to RxD HIGH Receiver delay symmetry
td(L),T td(H),T td(L),R td(H),R tsym,R
- - -
1 1 1
4 4 6
s s s
(LIN Spec 1.3; Line 10.3.6) (LIN Spec 1.3; Line 10.3.6)
CRxD = 20 pF; CRxD = 20 pF;
(LIN Spec 1.3; Line 10.3.7) (LIN Spec 1.3; Line 10.3.7)
-
1
6
s
-2
-
2
s
tsym,R = td(L),R - td(H),R
(LIN Spec 1.3; Line 10.3.8)
Data Sheet
44
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Transmitter delay symmetry Wake-up delay time TxD dominant time out TxD dominant time out recovery time Symbol Limit Values Min. Typ. - Max. 2 s -2 Unit Test Condition
tsym,T twake ttimeout ttorec
tsym,T = td(L),T - td(H),T
(LIN Spec 1.3; Line 10.3.9)
30 - 6 -
100 - 12 10
150 170 20 -
s s ms s
Tj 125 C Tj 150 C VTxD = 0 V VTxD = 5 V
Not subject to production test. Specified by design
Transfer Rate 20 kBit/s; 1 s < = RL x Cbus < 5 s Duty cycle D1 D1 0.396 - - duty cycle 1: THRec(max) = 0.744 x VS; THDom(max) = 0.581 x VS; VS = 7.0 ... 18 V; tbit = 50 s; D1 = tbus_rec(min)/[2 tbit] (LIN Spec 2.0; line 3.3.1) duty cycle 2: THRec(min) = 0.422 x VS; THDom(min) = 0.284 x VS; VS = 7.6 ... 18 V; tbit = 50 s; D2 = tbus_rec(max)/[2 tbit] (LIN Spec 2.0; line 3.3.2)
Rev. 1.51, 2007-06-22
Duty cycle D2
D2
-
-
0.581
Data Sheet
45
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Slew Rate falling edge "Low Slope/US Mode" Typ. - Max. -0.5 V/s 60% > Vbus > 40%; = RI x Cbus; 1 s < < 5 s; VS = 7 ... 18 V V/s 40% < Vbus < 60%; = RI x Cbus; 1 s < < 5 s; VS = 7 ... 18 V duty cycle 3 THRec(max) = 0.778 x VS; THDom(max) = 0.616 x VS; VS = 7.0 ... 18 V; tbit = 96 s; D3 = tbus_rec(min)/[2 tbit] (LIN Spec 2.0; line 3.4.1) duty cycle 4 THRec(min) = 0.389 x VS; THDom(min) = 0.251 x VS; VS = 7.6 ... 18 V; tbit = 96 s; D4 = tbus_rec(max)/[2 tbit] (LIN Spec 2.0; line 3.4.2) mA Unit Test Condition
Transfer Rate 10.4 kBit/s; 1 s < = RL x Cbus < 5 s
Sfslope
-1.5
Slew Rate rising edge "Low Slope/US Mode"
Srslope
0.5
-
1.5
Duty cycle D3
D3
0.417 -
-
Duty cycle D4
D4
-
-
0.590
Master Termination Switch Output; Pin MTS
Ron resistance
Maximum output current
Data Sheet
RonMTS IMTS
- 40
33 -
60 150
IMTS = -15 mA VMTS = 0 V
46
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Leakage current Symbol Limit Values Min. Typ. - Max. 5.0 A sleep mode; VMTS = 0 V -5.0 Unit Test Condition
IMTS,lk
Data Sheet
47
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. SPI-Interface Logic Inputs DI, CLK and CSN H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Typ. Max. Unit Test Condition
VIH VIL VIHY
- 0.3 x
- -
0.7 x
V V V k k pF
- - -
VCC1
- 1.5
VCC1
0.8 20 20 -
Pull-up resistance at pin RICSN CSN Pull-down resistance at RICLK/DI pin DI and CLK Input capacitance at pin CSN, DI or CLK Logic Output DO H-output voltage level L-output voltage level Tri-state leakage current Tri-state input capacitance Clock period Clock high time Clock low time Clock low before CSN low CSN setup time
40 40 10
80 80 15
VCSN = 0.7 x VCC1 VDI/CLK = 0.2 x VCC1
Not subject to production test. Specified by design
CI
VDOH VDOL IDOLK CDO
-0.4 - -10 -
VCC1
0.2 0.2 - 10
VCC1 - -
0.4 10 15
V V A pF
IDOH = -1 mA IDOL = 1.6 mA VCSN = VCC1; 0 V < VDO < VCC1
Not subject to production test. Specified by design
Data Input Timing Not subject to production test. Specified by design
tpCLK tCLKH tCLKL tbef tlead
250 125 125 125 250
- - - - -
- - - - -
ns ns ns ns ns
- - - - -
Data Sheet
48
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Symbol Limit Values Min. Typ. - - - - - - - Max. - - - - 50 50 10 ns ns ns ns ns ns s - - - - - - - 250 125 50 50 - - - Unit Test Condition
tlag tbeh tDISU tDIHO trIN
tfIN Input signal fall time at pin DI, CLK and CSN
Delay time for mode change from Normal Mode to Sleep Mode CSN high time DO rise time DO fall time DO enable time DO disable time
tfIN
tCSN(high) 15 trDO tfDO tENDO tDISDO
- - - -
- 30 30 - -
- 80 80 50 50
s ns ns ns ns
two oscillator periods
Data Output Timing Not subject to production test. Specified by design
CL = 100 pF CL = 100 pF
low impedance high impedance
Thermal Prewarning and Shutdown (junction temperatures) (Not subject to production test. Specified by design) prewarning ON temperature prewarning hyst. shutdown temp. temp.
VCC1 thermal VCC1 thermal
TjPW
T
120
145
170
C
bit 0 of SPI diagnosis word - hysteresis 35 K (typ.) -
- 155 -
25 185 1.20
- 200 -
K C -
VCC1/2 thermal
TjSD TjSD/ TjPW
VCC1 ratio of SD to PW
Data Sheet
49
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Table 13 Electrical Characteristics (cont'd)
VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 C < Tj < 150 C (max. 125 C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter OUTHS thermal shutdown temp. OUTHS thermal shutdown hyst. Symbol Limit Values Min. Typ. 175 10 - 10 - 10 Max. 200 - 190 - 190 - C K C K C K - - - - - - 150 - 150 - 150 - Unit Test Condition
TjSD
T
TjSD CAN Transmitter thermal shutdown temp.
CAN Transmitter T thermal shutdown hyst. LIN Transmitter thermal TjSD shutdown temp. LIN Transmitter thermal T shutdown hyst.
1) Vdiff = VCANH - VCANL
Data Sheet
50
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics Timing Diagrams
CSN high to low: DO is enabled. Status information transferred to output shift register CSN time CSN low to high: data from shift register is transferred to output functions CLK time Actual data DI FI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DI: will accept data on the falling edge of CLK signal Actual status DO FO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DO: will change state on the rising edge of CLK signal e.g. HS switch Old data Actual data
SPI_data_transfer_timing
New data FI 01 ++ time
New status FO 0 + 1 + time
time
Figure 12
SPI-Data Transfer Timing
Data Sheet
51
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics
Figure 13
SPI-Input Timing
Figure 14
Data Sheet
Turn OFF/ON Time
52 Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics
Figure 15
DO Valid Data Delay Time and Valid Time
Figure 16
Data Sheet
DO Enable and Disable Time
53 Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics
tWD tCWmax t CWmin
closed window
tOWmax tOWmin
open window
safe trigger area
0.4 0.6 0.8 1.0 1.2
t / [tWDPER]
tWWRP tWWRP : Window Watchdog Reset Period set via SPI, see table 9
Figure 17
Watchdog Time-Out Definitions
tCW WD Trigger tCW tOW
tOW tCW +tOW tLW tLW
tCW
tOW tCW
tLW tCW tOW
Reset Out
tWDR
t
Watchdog timer reset
t normal operation timeout (too long) normal operation timeout (too short) normal operation
Figure 18
Watchdog Timing Diagram
Data Sheet
54
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics
VCC
VRTx VCC1-Fail
t < tRR
WD Trigger
tRD1
tLW
tLW
tCW
tOW
tRDx
tLW
tCW
t
Reset Out
tWDRx
tRR
t
Watchdog timer reset
t start up normal operation undervoltage start up
VCC1 fail flag
tVCC, r
HIGH
LOW
t
activation by C [first SPI transmission]
Figure 19
Reset Timing Diagram
Data Sheet
55
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics
VTxD VCC
GND
VDIFF
td(L), T
td(H), T
t
VDIFF(d) VDIFF(r) VRxD VCC
0.7VCC 0.3VCC GND
td(L), R
td(H), R
t
td(L), TR
Figure 20
td(H), TR
t
AET02926
CAN Dynamic Characteristics Timing Diagram
Data Sheet
56
Rev. 1.51, 2007-06-22
TLE 7263E
Electrical Characteristics
VCC
VTxD
GND td(L),T VS td(H),T
t
Vbus
GND
Vbus,rd
Vbus,dr
td(L),R VCC
td(H),R
t
VRxD
0.3*VCC GND td(L),TR td(H),TR
0.7*VCC
t
Figure 21
LIN Dynamic Characteristics Timing Diagram
Data Sheet
57
Rev. 1.51, 2007-06-22
TLE 7263E
Application Information
7
7.1
Application Information
ESD Tests
Tests for ESD robustness according to IEC61000-4-2 "gun test" (150pF, 330) have been performed. The results and test condition are available in a test report.
Table 14
ESD "GUN test" Result
Unit kV kV Remarks
1)
Performed Test
ESD at pin CANH, CANL, LIN, Vs +8 versus GND ESD at pin CANH, CANL, LIN, Vs -8 versus GND
Positive pulse Negative pulse
1)
1) ESD susceptibility "ESD GUN" according LIN EMC 1.3 Test Specification, Section 4.3. (IEC 61000-4-2) Tested by external test house (IBEE Zwickau, EMC Test report Nr. 11-11-06).
Data Sheet
58
Rev. 1.51, 2007-06-22
TLE 7263E
Application Information
7.2
Application Example
60Ohms
Vbat CAN bus
4.7nF
60Ohms
SPLIT CANH CANL OUTHS MON4
1kOhm
FSO RxDCAN TxDCAN CSN CLK DO DI INT RO
MON3 MON2
10 kOhm
MON1
WKO STS
MTS VS
VCC1
100 nF
1 kOhm
68 F
TLE 7263
VCC2 TxDLIN RxDLIN LIN SI GND
100 nF
10 F
C
e.g. XC164CM
LIN Bus
VCC2
10 F
0.1 F
GND
1 nF
160 kOhm
100 kOhm
4.7 nF
Appl_7263
Figure 22
Application Circuit
Data Sheet
59
Rev. 1.51, 2007-06-22
TLE 7263E
Package Outlines
8
Package Outlines
0...0.15 STAND OFF 2.45 -0.2 2.65 MAX.
0.35 x 45
12
0.65 C 17 x 0.65 = 11.05 0.33 0.08 2) 0.1 C 36x SEATING PLANE
1.1
0.7 0.2 10.3 0.3 D
0.17 M A-B C D 36x A
19
Bottom View
19 36
36
5.1
Exposed Diepad
1
18
18
B 12.8 -0.21) Index Marking
7
1
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side
GPS01153
Figure 23
PG-DSO-36-24 (Plastic Dual Small Outline with Exposed Pad)
Green Product (RoHS Compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020)
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 60
Dimensions in mm Rev. 1.51, 2007-06-22
8 MAX.
7.6 -0.2 1)
0.23 +0.09
TLE 7263E
Revision History
9
Revision History
TLE 7263E Revision History: Previous Version: Page 40 Page 2 32/33 60 2007-06-22 Revision 1.50 Rev. 1.51
Subjects (major changes since last revision) Propagation Delay valus (td(L),T; td(H),T; td(L),R ; td(H,)R) changed. Preliminary Data Sheet 1.41 Subjects (major changes since last revision) New package picture Typical values added and update quiescent current; pin VS Latest package drawing
Previous Version:
Data Sheet
61
Rev. 1.51, 2007-06-22
Edition 2007-06-22 Published by Infineon Technologies AG 81726 Munchen, Germany
(c) Infineon Technologies AG 2007.
All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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